urgent openings for Verification Engineers!!! MULTIPLE LOCATIONS!!!

Hi,

We have got urgent openings for Verification Engineers. Please feel free to contact Julian George.
Email:--- jgeorge@ibisint.com

 

Client will hire by phone, 2 or 3 phone screens.

 

US Citizen, GC, or Perm Resident preferred!!!

 

 

 

Location	Austin TX
Title	SoC Verification Engineer
Length	6- 9 months
Process	Phone Hire (2 or 3 interviews)
Description	Verification engineer to work on the next generation high performance x86 SOC Verif testbench.
	Work on testbench porting, initialization, and tool integration. Duties involve bringing up a new SOC testbench
	environment. Debug compilation and x86 SOC simulation fails
	Contribute to the continuous improvement of verification environment and methodology.
	5+ years of experience in verification, preferably at the SOC level
	- software experience in C++, Perl, Verilog/SystemVerilog
	- experience with VCS/Verdi
	- familiarity with revision control systems such as Perforce
	- strong software debug skills and logic simulation debug skills
	strong communication skills.
	experience in unix environment
	- experience with x86 assembly and computer architecture knowledge is a plus
Location	Austin TX
Title	Verification Engineer
Length	6 - 9 months
Process	Phone Hire
Description	Lead the verification efforts of tester determinism across multiple client and server projects
	prove design under test will be deterministic on the ATE tester. Qualify and deliver full-chip stimulus for use in
	silicon ATE for product characterization and test.
	5+ years of experience in verification, preferably at the SOC level
	- software experience in C++, Perl, Verilog/SystemVerilog
	- experience with VCS/Verdi
	- familiarity with revision control systems such as Perforce
	- strong software debug skills and logic simulation debug skills
	- strong communication skills (position requires interaction with engineers at multiple international sites and frequent syncs with other team members)
	- experience in Unix environment
	- Background and interest in SoC post-silicon validation.
	- experience with x86 assembly and computer architecture knowledge is a plus
	- ATE, JTAG, and DFT experience is a plus
Location	Boxboro, MA
Title	Verification Engineer
Length	9 - 12 months
Process	Phone Hire
Description	Demonstrated technical experience in automating verification tools and flows for semiconductor designs.
	- Requires experience with Perl, and similar shell scripting.
	- Requires experience with automation of verification environments, simulators, makefiles, and source control systems such as CVS and Perforce.
	- Requires excellent communication and leadership skills.
	- Knowledge of automation for IP reuse and IP reuse methodologies highly desired.
	- Knowledge of functional verification, SystemVerilog, and typical simulation/logic design tools a plus.
	- Knowledge of C/C++ and language parsers a plus.
	- Knowledge of Ruby a plus
Location	Sunnyvale
Title	Verification Engineer
Length	6+ months
Process	Phone Hire
Description	7 or more years of direct verification
	Should have done gate sims on atleast 3 mixed signal design
	Gatesims with vcs simulator is a must
	Should be familiar with ddr protocol
	Prefer ddr phy knowledge
	Should be good in perl or python scripting, verilog, system verilog
	Prefer mixed signal gate sim
	Knowledge of ovm is a plus

--
Thanks & Regards..........
 

Julian George
IT Recruiter
IbisTech International (Formerly known as Hirange Technologies)
906 Lacey Avenue Suite 106
Lisle; Illinois;60532
Ph: 630 324 8509
Fax Number 630-969-2722
jgeorge@ibisint.com